
RFID reader integrated circuits (IC) combine many of the electronic components used in RFID interrogators (readers) on a single silicon microchip. They are designed to help engineers incorporate RFID technology into a wide variety of applications by simplifying design and reducing the need for a lot of complex discrete electronic components.
In this video interview for our more technical audience, Mark Dickson talks about austriamicrosystems innovative single chip reader solutions for UHF RFID and compare the austriamicrosystems RFID Reader IC Family.
The AS3992 UHF Gen 2 Reader chip is an integrated analog front-end and provides protocol handling for ISO18000-6b/c 900MHz RFID reader systems. Equipped with multiple built-in programming options, the device is suitable for a wide range of UHF RFID applications.
The AS3992 is pin to pin compatible with the previous AS3990/91 IC's. It offers improved receive sensitivity to -86dB, fully programmable Rx DRM filters on chip and pre-distortion. Fully scalable, the AS3992 is ideal for longer range and higher power applications.
Offering DRM compliance on chip, combined with improved sensitivity and pre-distortion allows the AS3992 to be the only true world wide shippable IC. The reader configuration is achieved through setting control registers allowing fine tuning of different reader parameters.
The AS3990/91 UHF reader chip is an integrated analog front-end and data framing system for a 900MHz RFID reader system. Built-in programming options make it suitable for a wide range of applications in UHF RFID systems. Designed to simplify the design and implementation of an EPC Class1 Gen2 reader, this IC requires only a standard 8-Bit microcontroller with minimal other components.
The AS3990/91 comprises the EPC Class1 Gen 2 protocol (ISO 18000-6c) with digital high speed logic up to the framing level and supports the ISO 18000-6a and ISO 18000-6b Protocol with direct data mode. The Interface to the microcontroller can be either a 4-pin serial data Interface (SDI) or alternatively in case of high data rates are necessary an 8-Bit parallel. The frame management will be done using a 12 Byte FIFO in order to decrease processor workload and ensure a smooth data stream and correct protocol handling. All low level transmission codecs and CRC generation is done internally.
For more information, visit austriamicrosystems.com.
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